In recent years, the market demand for large-capacity, low power consumption SDRAMs has increased as work memories for image processing and video processing in mobile telephones and mobile devices. Especially, in mobile devices, as it is integrated into SIP (System in Package) with a CPU more and more, the major reduction of the refresh current and consumption current is expected. In such a situation, a limit on the processing speed occurs from data transfer from a work memory to a flash memory and retransfer from the flash memory to the work memory, therefore the demand for non-volatile memory/non-volatile RAMs whose write speed and read speed are SDRAM interface compatible has increased. As candidates for such a non-volatile RAM, FeRAM/MRAM (Ferroelectric Random Access Memory/Magnetoresistive Random Access Memory) have been developed. In FeRAM, which utilizes ferroelectrics, high integration is difficult at this point, and so is realizing the capacity and speed of DRAMs. Furthermore, in MRAM, which utilizes non-volatile magnetoresistive, since a write magnetic field is generated, the necessary write current per bit is several mA order and the write current consumption is too big.
Meanwhile, as a programmable memory with a resistance element, phase-change element is a promising candidate as researches have been done in order to realize non-volatile RAM. Since the write speed of phase-change memories is slow, the specifications that show compatibility with low power SRAMs or flash memories are conventionally reported. Especially in the SRAM specifications, phase-change memories offer a big promise since low power consumption is realized and the write speed is faster compared with non-volatile memories or flash memories.
Phase-change memory is a non-volatile memory where the characteristic of chalcogenide materials (such as Ge, Sb, and Te) that go back and forth between an amorphous state (high resistance) and a crystalline state (low resistance) when heated is utilized. Generally it is changed between a high resistance state (RESET) and a low resistance state (SET) by the joule heat caused by electric current and the amount of time the heat is applied, and approximately several 10 s to 100 ns of write time is needed. For instance, the structure of a 64 Mb RAM using a phase-change memory that takes 120 ns to be driven into a low resistance state (SET time) and approximately 50 ns to be driven into a high resistance state (RESET time) is described in Non-Patent Document 1.
Phase-change elements are non-volatile memory elements, however, voltage and current are applied to a phase-change element by a read disturbance, and the resistance value of the phase-change element is changed, deteriorating the retention characteristics and read margin.
Similarly, it is known that, because of the voltage and current applied to a phase-change element by a similar disturbance when being written to, the resistance value change will deteriorate over time. FIG. 6 is a drawing showing the resistance value change of a phase-change element caused by read/write operations. The abscissa indicates how many times read/write operation has been performed, and the ordinate shows the resistance values of the phase-change element when it is SET/RESET. The more read/write actions are performed, the more the element resistance value decreases.
Meanwhile, a semiconductor memory device that delays the timing of a write operation to a memory cell upon receiving a write request in the write operation of a volatile synchronous SRAM is known (for instance refer to Patent-Documents 1 and 2). Such a method is called late write method, and write operations can be performed stably.
[Non-Patent Document 1]
Woo Yeong Cho, et al. “A 0.18 μm 3.0V 64 Mb Non-Volatile Phase-Transition Random-Access Memory (PRAM),” 2004 IEEE International Solid-State Circuits Conference, ISSCC 2004, SESSION 2, NON-VOLATILE MEMORY, 2.1, Feb. 16, 2004.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-8-45277
[Patent Document 2]
Japanese Patent No. 2888201